1. Field of the Invention
The present invention relates in general to bus arbitration apparatus for computer systems. In particular, the present invention relates to an apparatus for programmable multi-level bus arbitration for computer systems. More particularly, the present invention relates to a programmable multi-level bus arbitration apparatus for microprocessor-based computer systems capable of allowing bus master devices with higher priority to interrupt other masters for real-time applications.
2. Technical Background
In typical microprocessor-based computer systems, there are occasions when bus master devices residing on the system bus need to take immediate control of the system to execute specific computing tasks. Typical prior art computer systems allow a bus master device to maintain continuous control over the entire system until it concludes its task, or its assigned time slot in its mastering cycle expires and it relinquishes control of the bus.
Frequently, certain bus master-initiated tasks require an extended time period to process the tasks. In order to maintain the entire computer system in a smooth operating mode, some prior art computer systems employ a bus arbitration strategy which limits the maximum time period a bus master can occupy the entire system. Once the set time period expires, any master device must surrender control of the bus back to the system, whether or not it had completed its intended task. The unfinished task can only be continued when the bus arbiter of the system grants it control over the bus again.
Such mandatory interruption of bus mastering tasks is necessary to sustain proper operation of the computer system. The typical microprocessor-based computer system has certain house-keeping operations that must be taken care on a timely basis. For example, main memory blocks of the computer system, which usually consist of arrays of dynamic random access memory chips, require periodic "refreshing" to prevent data bits contained therein from disappearing. Similarly, a communication processing hardware subsystem in the computer system can not break line connection for an extended period of time without losing information bits it is supposed to receive.
However, this prior art scheme of bus control arbitration based on a fixed time period for all bus mastering tasks is not suitable for certain applications involving real-time data processing by the system. Certain computation-intensive real-time applications, such as video and audio processing, as well as power conservation management of the computer system, typically require almost immediate processing by either the central processing unit (CPU) of the system or any bus master residing on the system bus. Failure to attend to the needs of these processing requirements might lead to system malfunction.